By Mohammad Tehranipoor, Ke Peng, Krishnendu Chakrabarty
This e-book will introduce new thoughts for detecting and diagnosing small-delay defects in built-in circuits. even supposing this kind of timing illness is often present in built-in circuits synthetic with nanometer expertise, this may be the 1st booklet to introduce powerful and scalable methodologies for screening and diagnosing small-delay defects, together with very important parameters corresponding to strategy adaptations, crosstalk, and gear offer noise.
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Extra resources for Test and diagnosis for small-delay defects
Sample text
However, smaller pattern counts mean lower test quality in most cases, especially for newly emerged defects such as small-delay defects (SDDs). In fact, many companies use n-detect pattern set, which in turn result in much larger pattern 18 1 Introduction to VLSI Testing counts, compared with 1-detect pattern sets, to ensure high test quality. This book presents techniques to reduce pattern count while keeping a very high test quality for screening SDDs. References 1. A. Krstic and Kwang-Ting Cheng, “Delay Fault Test for VLSI Circuits”, Boston: Kluwer Academic Publishers, 1998 2.
Auth, “Improved Deterministic Test Pattern Generation with Applications to Redundancy Identification”, in IEEE Trans. on Computer-Aided Design, vol. 8, no. 7, pp. 811–816, 1989 References 19 22. M. H. Schulz and E. Auth,, “SOCRATES: A Highly Efficient Automatic Test Pattern Generation System”, in IEEE Trans. on Computer-Aided Design, vol. CAD-7, no. 1, pp. 126– 137, 1988 23. M. J. Y. Willaims and J. B. Angell, “Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic”, in IEEE Trans.
Depending on how the transition is launched and captured, there are three transition fault pattern generation methods, referred to as launch-off-shift (LOS) or skewed-load [12], launch-off-shift (LOC) or broadside method [11], and Enhanced Scan [3]. For the LOS method, the transition at the gate output is launched in the last shift cycle during the shift operation. Then the scan enable (SEN) goes low to enable response capture at the capture clock edge. 8 shows the LOS waveform for a scan flip-flop design.