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Additional info for Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia
Example text
The same set of input vectors used in [4] and [5] for power estimation was converted from SLS to SPICE format and then used for transient analysis. The timing analysis tool PrimeTime [12] was used to estimate the critical delay of the circuits. PrimeTime is able to perform both static and functional timing analysis. Static timing analysis (STA) is the standard approach used for delay estimation in the current designs complexity. The main issue of this approach is that logic information about the cells of the circuit is not considered during the critical delay search.
These so called frames are the atomic unit of configuration and are addressed by the major address (MJA) and the minor address (MNA). A detailed description can be found in [11]. The columnwise reconfigurability of the Virtex FPGAs also inspired our reconfigurable system approach [7]. All hardware tasks can be dynamically placed, relocated and erased along a horizontal communication infrastructure (1D-placement). The communication infrastructure is completely homogeneous, which makes it possible to dynamically relocate hardware tasks along the horizontal bus structure.
P. 424 7. T. S. Messerges and E. A. Dabbish, R. H. Sloan, “Investigations of Power Analysis Attacks on Smartcards”, USENIX Workshop on Smartcard Technology, Chicago, Illinois, USE, May 10-11, 1999. 8. Marc Renaudin, “Asynchronous circuits and systems: a promising design alternative”, Microelectronic for Telecommunications : managing high complexity and mobility” (MIGAS 2000), special issue of the Microelectronics-Engineering Journal, Elsevier Science, GUEST Editors : P; Senn, M. Renaudin, J, Boussey, Vol.