By Bradly K. Fawcett
A close research of the 16-bit microprocessor emphasizing good judgment layout with the Z8001 and Z8002 microprocessors. different parts within the Z8000 kin of elements are mentioned. worthwhile to an individual attracted to studying in regards to the Z8000 who has had a few event with microprocessors and knows recommendations similar to registers, buffers, software counters, and interrupts.
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Extra resources for The Z8000 microprocessor: A design handbook
Example text
Thus these signals, together with the RESET line, define the Z-Bus interface to peripheral devices (Fig. 1). The Z8000 CPU accesses peripherals in a manner similar to memory accesses. The start of a CPU-peripheral data transfer is signaled by AS going low (Fig. 2). The status signals (which should indicate standard or special I/O status) and the peripheral address on the address/data bus are guaranteed to be valid at the rising edge of AS; this edge can be used to latch these signals, if necessary.
1s; therefore, the slowest allowable clock rate is 250 kHz. A TTLgenerated clock signal is not adequate to drive the Z8000; active drivers are required to meet the stringent level, rise-time, and fall-time requirements. 4 V below the +5-V power input. Rise and fall times cannot exceed 20 ns for the 4-MHz parts and 10 ns for the 6-MHz parts. 14 shows a clock driver circuit for the 4-MHz Z8000. A 4-MHz square wave is generated by dividing an 8-MHz crystal oscillator with a toggling flip-flop. A resistive pull-up could ensure the required clock-high level but cannot guarantee the required rise time while driving the chip's 50-pF input capacitance.
All reads and word writes will cause both byte banks to be selected, whereas byte writes cause either the even-addressed bank of bytes or the odd-addressed bank to be selected, depending on ADO. For clarity's sake, the AS, DS, R/W, and WAIT connections between the Z8002 and the Z6132's are not shown in Fig. 18. The BUSY output of the Z6132's could be ORed with the output of the wait-state generator to produce the WAIT signal back to the CPU. Again, buffering of the signals from the CPU is necessary but is not shown here.