By Z. Peng, M. Sonza Reorda, M. Violante (auth.), Professor Matteo Sonza Reorda, Professor Zebo Peng, Dr. Massimo Violante (eds.)
New production applied sciences have made attainable the combination of whole platforms on a unmarried chip. This new layout paradigm, termed system-on-chip (SOC), including its linked production difficulties, represents a true problem for designers.
As good as giving upward thrust to new layout practices, SOC can also be reshaping techniques to check and validation actions. those are commencing to migrate from the normal register-transfer or gate degrees of abstraction to the process point. before, try and validation haven't been supported through system-level layout instruments so designers have lacked the mandatory infrastructure to take advantage of all of the advantages stemming from the adoption of the method point of abstraction reminiscent of larger sensible functionality and larger working pace. study efforts are already addressing this issue.
System-level try out and Validation of Hardware/Software Systems offers a cutting-edge review of the present validation and try innovations by way of overlaying all elements of the topic including:
• modeling of insects and defects;
• stimulus new release for validation and attempt reasons (including timing errors;
• layout for testability.
For researchers engaged on system-level validation and checking out, for device proprietors excited about constructing hardware-software co-design instruments and for graduate scholars operating in embedded platforms and SOC layout and implementation, System-level try and Validation of Hardware/Software Systems can be a useful resource of reference.
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Additional resources for System-level Test and Validation of Hardware/Software Systems
Sample text
12 shows the source code sketching it. Test Generation: A Symbolic Approach 43 class ControledGaussianSequence : public ControlBasedSequence { public: void init() { Control-BasedSequence::init(); InitDataBit(); } void InitDataBit(); ... 12. 1. For each benchmark three different data sizes (8, 16, and 32) have been considered as shown in Column 2. Columns 3−5 report respectively the number of bits for PIs, primary outputs and internal signals and variables. Then Column 5 and Column 6 show the number of gates and memory elements for every design.
Events are faulted in two different ways: by changing the eventual parameter of the notify method and by avoiding the event notification. Parameter modification is already modeled by the bit coverage fault model, since the parameter is an sc_time variable or constant. On the other hand, notification avoidance is obtained inserting an extra conditional statement. • Channels failures. Channels are similar to ports and signals from the fault model point of view. They can be faulted by modifying data managed by channels methods.
1 The Random-based Approach Generally, random-based ATPG [14,21] works in the following way: 1. An input sequence is generated in a random way or by exploiting some heuristic. For example, in the case of a GA-based ATPG, heuristics are represented by the fitness function used to guide the test pattern generation. 2. The sequence generated is applied to the fault-free DUT and to all of its faulty instances obtained by injecting, one by one, every fault modeled. 3. The outputs of the fault-free and of the faulty DUTs are compared for every fault modeled.