Read Online or Download [Magazine] IEEE Design & Test of Computers. 2007. September-October PDF
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Additional info for [Magazine] IEEE Design & Test of Computers. 2007. September-October
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It seems that the future of GALS methods is coupled with the future of NoCs. If the NoC concept fails, the chance of practical GALS applications will certainly be smaller. On the other hand, a NoC boom will lead to increased application of GALS systems. Low-power systems The GALS methodology has not yet proven itself as a way to achieve significant power savings at the SoC level. The only possibility for significant improvement over synchronous low-power methods is a combination of GALS-based systems with voltage and frequency scaling.
Singh, ‘‘An Architecture and a Wrapper Synthesis Approach for Multi-Clock Latency-Insensitive Systems,’’ Proc. Int’l Conf. Computer-Aided Design (ICCAD 05), IEEE CS Press, pp. 1006-1013. 5. T. M. Nowick, ‘‘Robust Interfaces for MixedTiming Systems,’’ IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, Aug. 04, pp. 857-873. 6. M. , ‘‘Xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for MultiProcessor SoCs,’’ Proc. 21st Int’l Conf. Computer Design: VLSI in Computers and Processors (ICCD 03), IEEE CS Press, 2003, pp.
We used it to perform all the experiments reported in the following section. Case studies To validate the functionality of our adaptive LIP, we implemented two systems which we chose as representatives of two extremes: a simple microprocessor (whose communication profile is extremely data dependent and related to the executed code) and an MPEG encoder (which presents a relatively uniform, burst type of communication). Microprocessor We described in VHDL code an extremely simplified, five-stage pipelined processor.