By Massimo Alioto
This booklet presents a unified remedy of Flip-Flop layout and choice in nanometer CMOS VLSI platforms. The layout features concerning the energy-delay tradeoff in Flip-Flops are mentioned, together with their energy-optimal choice based on the unique program, and the distinctive circuit layout in nanometer CMOS VLSI structures. layout suggestions are derived in a coherent framework that incorporates explicitly nanometer results, together with leakage, structure parasitics and process/voltage/temperature adaptations, as major advances over the prevailing physique of labor within the box. The similar layout tradeoffs are explored in a variety of purposes and the comparable energy-performance goals. a variety of latest and lately proposed Flip-Flop topologies are mentioned. Theoretical foundations are supplied to set the degree for the derivation of layout guidance, and emphasis is given on useful facets and effects of the provided effects. Analytical types and derivations are brought while had to achieve an perception into the inter-dependence of layout parameters less than sensible constraints. This booklet serves as a helpful reference for training engineers operating within the VLSI layout quarter, and as textual content e-book for senior undergraduate, graduate and postgraduate scholars (already conversant in electronic circuits and timing).
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Extra info for Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy
Sample text
11 Transmissiongates and/or pass-transistors network (a) and reduction to an equivalent RC tree (b) 23 (a) INTG,1 INTG,3 PUN with driving capability INTG,2 W WTG,1 X Y WPT,2 WTG,1 WTG,3 Z WTG,3 PDN with driving capability INTG,1 (b) R PUN/PDN CW INTG,3 R TG,1 CX R PT,2 CY RTG,3 CZ normalized capacitance nearly equal to ð3=2Þw (w is its normalized width) on both its source and drain nodes. Finally, note that when considering a structure such as that depicted in Fig. 11, the critical input can be one of those driving the PDN/PUN in the gate with driving capability, or one of those enabling a TG (or PT).
1 In order to include the parasitic capacitances due to local interconnects (within the logic gate) at the input and the output of the gate, let us introduce parameters zin and zout that weigh2 parasitic capacitive contributions through the gate size w. 2) becomes  à 2 EDYN ¼ ð1 þ s þ zin Þasw;in þ ð1 þ s þ zout Þasw;out w Á CT Á m Á VDD ð2:4Þ A similar analysis concerning the static dissipation of a CMOS gate can be carried out. , bsub;n þ bsub;p ¼ 1). 5), the parameter h accounts for the percentage of time spent in active and standby mode by the module that the considered gate belongs to.
The first (and at first glance the most appropriate) composite metric to be introduced is the simple ED product, which equally weighs the two quantities. Another popular metric is the ED2 product where speed has priority over energy. The latter metric is claimed to have useful properties such as a nearly zero sensitivity on the supply voltage [80]. , minimizing) the above metrics are maximally efficient for a given delay (or energy), it is clear that a generalization is required when exploring and designing a circuit over the entire spectrum of the delay (energy) values it can achieve.