By P. Conte
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Example text
3. Furthermore, this section also discusses the problems of quantitative approaches when evaluating debugging algorithms. 4 explains the proposed fault model for bugs in SystemC designs offering a possibility for evaluation and comparison of debugging methods. In Sect. 5 the applicability and accuracy of the debugging procedure for SystemC designs is evaluated using the formerly described fault model. In Sect. 6 we give a conclusion. 2 Preliminaries In this section some essentials of source code analysis are briefly reviewed.
For a given SystemC specification counterexamples are simulated to generate traces. The intersection of these traces includes and localizes the faulty statement. However, this is assured only if the design contains only a single bug. 3 General Idea and Discussion The debugging process is comprised of collecting information from the failed simulation trace or counterexample and analyzing the design until the error source is identified. In the meanwhile several debugging algorithms and strategies exist but comparing the algorithms is difficult.
In Sect. 3 the formal mapping relation between the object-oriented and the function network model is presented. The chapter closes with a use-case in Sect. 4 that demonstrates the application of the mapping and detection of timing violations in the formal model. 1 Executable Model – OSSS Design Methodology In the following, a brief overview of the SystemC-based OSSS methodology is given. We focus on the early phases of the OSSS design flow. A more detailed introduction can be found for example in [6].