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Extra resources for Springer-Verlag Creating Assertion-Based IP
Transactors are typically characterized by having at least one pin-level interface and at least one transactionlevel interface. Assertion-based IP (monitors) fall into this testbench architectural layer. , 2006] [eRM 2005], and you might have your own ideas for testbench architectural organization. Certainly we could spend hours debating the merits of various testbench organizations and architectural views. That is not the goal of this chapter. Our goal is to present an organizational view to set a framework for discussion throughout the remainder of the book.
Monitor_mp monitor_mp ); parameter DATA_SIZE parameter ADDR_SIZE = 8; = 8; bit [ADDR_SIZE-1:0] bus_addr; bit [DATA_SIZE-1:0] bus_wdata, bus_rdata; bit bus_write; . . clk) begin bus_addr bus_wdata bus_rdata bus_write . . end . . write; Thus far, we have seen how an interface is used (that is, referenced) inside a module-based component. To complete the connection of our interface, the signals must be accessible to class-based transactor components, such as the driver shown in Figure 3-2. For our testbench class-based components, we encapsulate them within a special class known as an environment class (see Appendix B, Chapter 3, “The Process” 47 “Complete OVM/AVM Testbench Example” for details), which is then instantiated within our top-level module (see env in Example 3-4).
The first section builds a framework for our discussion by introducing common verification components found within contemporary simulation environments. Understanding how the various verification components potentially interact and the communication channels required to connect these components is critical as we architect our assertion-based IP solution. The second section of this chapter provides a set of definitions for many terms used throughout this book. In addition, we spell out a list of common acronyms related to our topic.