The discharge of this moment quantity of CHIPS 2020 coincides with the fiftieth anniversary of Moore’s legislation, a severe yr marked through the top of the nanometer roadmap and through a considerably decreased annual upward thrust in chip functionality. whilst, we're witnessing an information explosion within the web, that is eating forty% extra electrical energy each year, resulting in fears of a tremendous blackout of the web through 2020.
The messages of the 1st CHIPS 2020, released in 2012, involved the conclusion of quantum steps for making improvements to the power potency of all chip services. With this moment quantity, we evaluation those messages and enlarge upon the main promising instructions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, mind- and human-vision-inspired processing, and effort harvesting for chip autonomy. The staff of authors, enlarged via extra global leaders in low-power, monolithic 3D, video, and Silicon brains, provides new vistas in nanoelectronics, promising Moore-like exponential progress sustainable via to the 2030s.
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Extra resources for Chips 2020, Volume 2: New Vistas in Nanoelectronics (The Frontiers Collection)
With regeneration and drive at the gate outputs, transmission-gate logic is possible with minimum transistor count (all-NMOS with low threshold voltage). A key example is the carry-generation gate in a differential transmission-gate CMOS adder (Fig. 8). At the heart of this gate is the “Quad”, the cross-coupled pair of CMOS inverters, which is treated in  and, with all its applications, in . 4 pJ/operation in a 800 nm technology. 1, more than 12 years later. It was projected in  that this type of sub-threshold, VDD Cout Propagate Cout Quad Propagate Cin Cin Generate Kill GND Fig.
In: 2012 IEEE International Solid-State Circuits Conference (ISSCC), Digestive Technology Papers, pp. 492–493, Feb 2012 19. 1, pp. 10–14, Feb 2014 20. : The Cross-Coupled Pair, Part I, Solid-State Circuits Magazine. Part II, Solid-State Circuits Magazine, Fall 2014, pp. 2–12 (2014) 21. : Exascale Computing—Fact or Fiction? SSCS Webinar (2014) Chapter 2 The Future of Low-Power Electronics Toshiaki Masuhara Abstract The number of integrated transistors has increased so rapidly that it has become evident that a further increase of the performance is limited by the power dissipation.
3V 1 Active Active Standby Standby Fig. 37 V  (© 2013 IEEE). a Cross-section of the SOTB transistor. b SEM Photo of the SRAM cell. c Access time of the SRAM. d Fail-bit of the SRAM as a function of Vdd. 3 V is applied . Although several SRAM circuit techniques were developed to operate the SRAM at low voltage, this demonstration was simply done by using the conventional 6-transistor SRAM cell without any voltage-boosting techniques for the word- and bit-lines to compare the technologies.